A low-cost ceramic BGA package for 50 Gb/s multiplexing circuit

In this work, standard multi-layer ceramic (Alumina) BGA packages were designed and fabricated to accommodate a 50Gb/s flip-chip multiplexing circuit built on SiGe BiCMOS technology. The ceramic packages are of the size of 17/spl times/17 mm/sup 2/ with 8 layer internal stacks, C4 bonding pads on top, and BGA solder joints at the bottom. For comparisons and various application needs, the high-speed output nets were routed with two approaches, "surface coaxial escape" and "through BGA escape". In the case of "through BGA escape", special via structures were designed to optimize the signal transmissions within a wide frequency range, DC/spl sim/50GHz. To test the performance of the package, two types of test carriers were designed and fabricated on low-loss organic boards, one with edge-mount coaxial connectors for full functional tests, and the other with probe sites for through BGA characterizations in both frequency and time domains. Prior to the physical layout of the designs, electrical analysis was performed with segmentation and re-assembling technique that employs full-wave EM simulations. The results were then compared with measurements, and effective model-to-hardware correlations were found. The existing measurement results indicate that, by properly design the critical nets, standard multi-layer BGA packages can be used for high-speed applications up to 40/spl sim/55Gb/sec data-rate/frequency range.