Boolean minimization using new ATPG techniques and saved test patterns

An enhanced approach to the Boolean minimization of a combinational logic circuit is described. The approach uses random automatic test pattern generation (ATPG) and recent developments in deterministic ATPG techniques, and reuses saved test patterns to eliminate additional calls to RATPG and DATPG. Modifications to a previous approach are presented, as well as the enhancements to the new DATPG method. The resulting minimization program can solve problems that the previous method could not, and can solve others up to 2000 times faster.<
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