Defect analysis and test generation for gate oxide shorts in CMOS ICs

A test pattern generation algorithm for testing each type of gate to detect gate oxide short defects (605 in all) of the transistors composing it is presented. It is concluded that only the preceding logic is important as far as test generation is concerned, because it involves application of a test vector so as to provide a path from V/sub dd/ to ground through the gate of the transistor under test. After iterating through all the possible input logic combinations, generalized rules can be formulated. Results obtained for PFET and NFET showed symmetry; in other words, the same conditions were obtained for all P-type transistors of the gate under test, and such was also the case with the N-type transistors.<
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