A video rate rerastering IC

A video mapping IC developed for the real-time compression and expansion of raster-scanned video lines in the generation of NTSC-compatible HDTV signals is described. The circuit is implemented with standard cells and contains 70000, 1.5 mu m, CMOS transistors. The device performs a four-point nonlinear interpolation, contains a 200 pixel dual-port RAM, is serially configurable, and operates at 14.3 MHz. Simulation was used to determine subjective acceptable interpolation resolution. A FORTRAN program was written to implement the peaked interpolation algorithm.<
>