A sub-10 ns cache SRAM for high performance 32 bit microprocessors

A high speed cache SRAM with an output enable access time of 8 ns has been built using a 0.9 mu m CMOS technology. The cache memory is configurable and can be used as either an 8K*16 in the direct mapped mode, or in a two-way set-association mode as a 2*4K*16 memory for higher cache hit rates. The cache SRAM works directly with the 82385 cache controller from Intel in a 33 MHz 80386 system. A high-speed static RAM designed to provide an easy-to-implement cache memory for high-performance microcomputers is described.<
>