A high performance one micron CMOS technology chip

A high-performance, semicustom, 9.44 mm*9.35 mm chip built on one micron CMOS with two levels of metal is described. Pulse distortion and delay were the limiting design factors. A practical limit of 96 MHz was specified on all critical nets due to pulse distortion. Custom macros were designed and used in critical areas to limit pulse distortion and to meet tight delay tolerance specifications. Wiring capacitance was specified to be limited to 0.5 pF/fanout with a maximum of three fanouts per output stage. Only logic books having buffered output stages were used in critical nets. Capacitive loading constraints required manual intervention in the placement and wiring process.<
>