A full 1.2 mu m CMOS ECL-CMOS-ECL converter with subnanosecond settling times

A full 1.2 mu m CMOS circuit which converts digital signals from ECL to CMOS and vice versa is presented. High performances are obtained due to the use of only NMOS devices in the signal path, replica biasing for accurate control of the signal levels, and charge injection to ensure extremely steep edges and subnanosecond settling times. To test and demonstrate the possibilities, a full CMOS ECL-compatible repeater for a broadband ISDN switching board has been designed: the attenuated ECL signal is converted in CMOS levels, stored in a high-speed CMOS flip-flop (which represented CMOS logic), and finally converted back into an ECL signal. The system can detect and drive 75 Omega interconnected lines as long as 15 m. The total system has two clock slices (clock and clock inverse), four data slices and one frame slice.<
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