Effect of device and interconnect scaling on the performance and noise of packaged CMOS devices

A detailed investigation of the effects of device and interconnect scaling on CMOS performance and noise was performed for multilayer packages. Results of simulations using experimental scaled-device data for one micron and two micron L/sub eff/, and recently developed modeling tools for interconnect parasitics, were obtained. These results were compared to predicted performance and noise characteristics obtained using conventional constant-voltage scaling schemes. Significant differences were found.<
>