A mixed level simulator mega-FAL with novel data structure oriented to HDL statements

The VLCAD functional design subsystem, which consists of a mixed-level simulator, a logic synthesizer, and a functional test generation assistant, has been developed as a solution to the problem of reduction of design time in VLSI design. Application of the VLCAD to many VLSI products showed that it reduced the system design time by half. There is a need for a more efficient CAD system in order to serve more than megagate-class system design. A novel functional design database is proposed to unify the above tools in order to facilitate the design activity using the VLCAD system. A novel mixed-level simulator that runs faster than a previous mixed-level simulator using the functional design database is also developed.<
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