A 150 K-circuit ASIC family using a DRAM technology

The features of a gate-array ASIC family using a CMOS DRAM technology are described. The availability of DRAM, the mix of gate-array and standard-cell circuits, and the choice of using either DLM (double-level metal) or TLM (triple-level metal) provide a designer with options not available in other ASIC families. The associated design system enables design entry, physical design, design verification, and release to manufacturing with as little manual intervention as possible. By using this ASIC family and design system, high-performance chips with up to 253 K-circuits can be designed. This family has been demonstrated with a 128 K-circuit chip.<
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