Data-flow analysis in superscalar computer architecture execution

This paper treats the problem of detection of data hazards in superscalar execution. The algorithms of independent instruction detection are represented. They can be used in out-of-order execution logic and code optimised algorithms. The first algorithm uses the platform of Intel Pentium architecture and analyse the IA-32 instruction set. The algorithms is implemented in a software simulator, which represents the way the Intel Pentium processor works. They can be used in software module, which simulates out-of-order execution logic.