Energy and timing characterization of VLSI charge-pump phase-locked loops

Phased locked loops (PLLs) are frequently employed in high-speed communication links, RF demodulation systems and SOCs for frequency synthesis. As wireless portable systems become standard, performance and power PLL models are essential in order to explore design trade-offs and feasible power reductions. We present a PLL timing model, review results of our power model and couple them with expressions for jitter estimation. The model has been validated and shown to be within 5% of circuit level simulation numbers.