Implementation of high-speed blind channel equalizer for QAM modems

This paper proposes a decision feedback equalizer (DFE) with an error feedback filter using the multi-modulus algorithm (MMA). The proposed equalizer has been designed for 64/256 QAM modulations. The proposed DFE adds the error feedback filter to the DFE structure to improve the channel adaptive performance. We have simulated the proposed equalizers using the Cadence/spl reg/ SPW/spl trade/ CAD tool. The architecture has been modeled by VHDL and logic synthesis has been performed using the 0.25 /spl mu/m Faraday library. The total gate count of the proposed equalizer is about 190,000 and the operating frequency is 15 MHz. The proposed equalizers provide a symbol rate up to 64 Mbps.