A low-voltage loadless 4N SRAM with smart hidden refresh

This work describes a smart hidden refresh scheme for designing embedded 4N SRAM. An improved dynamic NOR decoder is also presented to achieve high-speed and low-power operation at low supply voltage. The smart refresh scheme can overcome the performance limitations of the conventional hidden refresh scheme. The new design has the same I/O specification as that of 6T SRAM. It can be fabricated in standard CMOS processes as a small-area embedded memory. A test chip of 256/spl times/8 cells performs at 77 MHz at a supply voltage of 1.2 V. The area is 25% less than that of the 6T SRAM.