A delay-line based DCO for multimedia applications using digital standard cells only

A digital clock synthesizer consisting of digital standard cells with 0.5ppm frequency resolution for multimedia applications is implemented in a 0.6/spl mu/m CMOS process. The synthesizer produces an output frequency ranging from 11.1MHz to 12.5MHz with a 100MHz input clock. A DLL-based calibration mechanism tracks PTV variations during operation.