A 700/900mW/channel CMOS dual analog front-end IC for VDSL with integrated 11.5/14.5dBm line drivers

A dual-channel analog front-end for ANSI/ETSI standards compliant VDSL in 0.25/0.5μm 1P 5M CMOS is presented. The chip includes a non-linearity cancelling multi-path line driver achieving -76dBc 3rd harmonic distortion at 12MHz, a 75mW continuous-time multi-bit 3rd-order self-calibrating ΣΔ ADC, a 14b current-steering DAC with PSD mask post filter, a 0-35dB variable-gain amplifier with adjustable hybrid, and a 12ps jitter LC PLL.