A 2 GS/s 6 b ADC in 0.18 /spl mu/m CMOS

A 2 GS/s 6-bit ADC with time-interleaving is demonstrated in 0.18 /spl mu/m CMOS. Three cross-connected and pre-distorted reference voltages improve the averaging performance. Circuit techniques enabling an SNDR of 30 dB at Nyquist input frequency and a FOM of 3.5 pJ per conversion step are discussed, and experimental results validating the simulated performance metrics are presented.