Grain boundary effects on subthreshold behaviour in single grain boundary nano-TFTs

A simulation model for deep trap states at grain boundaries in Poly-Si TFTs is developed. The model is used for simulation of single GB TFT devices with sub micron channel lengths. The transport physics is clarified and it is found that in short channel devices (L/sub eff/<100 nm) the single GB TFT shows improved subthreshold behaviour compared to its SOI equivalent.