Simulation of surface engineering for ultra shallow junction formation of PMOS for the 90nm CMOS technology node and beyond

Since the junctions in the most advanced CMOS devices are thinner and thinner, the influence of the surface of silicon is thus becoming significant on dopant diffusion. In this paper, based on experimental data, a methodology for calibration is proposed, taking this effect of surface into account. SIMS profiles are accurately fitted by simulation using a simple model of recombination of interstitials; the phenomenon of POED is well reproduced and validated by TCAD ID simulations. Then, the impact of POED on the PMOS performances is quantified by anticipation with 2D TCAD simulations.