OASYS: a framework for analog circuit synthesis

A description is given of a hierarchical structure for a knowledge-based analog circuit synthesis tool. Analog circuit topologies are represented as a hierarchy of abstract functional blocks, each with associated design knowledge. The author also describes mechanisms for selecting from among alternate design styles and translating performance specifications from one level in the hierarchy to the next lower level. A prototype implementation, OASYS, synthesizes sized transistor schematics for CMOS operational amplifiers and comparators from a set of performance specifications and process parameters. The role such a synthesis system can play in exploring the space of designable circuits is examined.<
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