A GaAs 600 Mbit/s 24B1P coder/decoder ASIC

The technical details, tradeoffs, and economics associated with the design of a gallium arsenide 600-Mb/s 24B1P coder/decoder ASIC (application-specific integrated circuit) are reviewed. Key features of the design include the use of common components to allow integration of encoder and decoder on the one chip, a novel data accelerator/decelerator, and the use of asynchronous control circuitry. The ASIC is evaluated in terms of both complexity and effort in relation to designing with gallium arsenide standard cells. An improved design that can operate at rates in excess of 1.3 Gb/s is presented.<
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