Estimating the utilization of embedded FPGA co-processor

Embedded FPGA co-processors will bring new alternatives for SoC system designers. Comparison of software implementations and reconfigurable hardware implementations will need fast and easy-to-use estimation techniques. In this paper, we present an estimation approach for the resource utilization of the embedded FPGA co-processor. Our approach is based on the principles of high-level synthesis, such as force-directed scheduling, resource allocation, operation assignment and interconnection binding. The method has been applied to simple test cases and a C-language model of MPEG-2 decoder. The average hardware estimation error of MPEG-2 functions was 25%.