A 1.3 mu m BiCMOS gate array with configurable on-chip 3-port RAM

A 10 K-gate BiCMOS gate array with a configurable 4.6-kb SRAM (static RAM) has been developed using a 1.3- mu m technology. The propagation delay time of a two-input NAND is 0.45 ns at 0.6-pF load. The on-chip memory can be configured as *9, *18, *36 b. A description is given of the device structure, the basic cell design, the memory configuration, and the performance of this memory-plus-logic combination.<
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