A high throughput, asynchronous, dual port FIFO memory implemented in ASIC technology

An ASIC (application-specific integrated circuit) first-in-first-out (FIFO) memory circuit that has the capability of interfacing two data processing units operating at different speeds is described. The memory is implemented using a circular queue structure, which permits writing and reading of data indefinitely as long as the boundary flag conditions are not met. This memory also has the capability to retransmit only bad data words, not whole memory blocks as most standard FIFOs do. Another feature is dual-port memory operation, which allows bidirectional data transfers through the FIFO. All of the circuit implementations are done using NCR standard cells. This allows the use of automatic routing and test program generation tools provided by NCR VISYS.<
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