Examination and improvement of reading disturb characteristics of a surrounded gate STTM memory cell

This paper introduces a novel surrounded gate STTM cell technology to improve retention and read disturb characteristics. In the memory cells previously reported, the device structures limits the CMOS-compatible memory integration and the operation voltage scaling of the memory cells. The proposed cell architecture overcomes this problem and also improves the read disturb characteristics. The proposed memory cell was fabricated using the 0.18 um design rule based on the low power SRAM process technology. This paper demonstrate an the device characteristics of the proposed memory cell and the improvement of tin a read disturb characteristics.