Electrical characterization of SiO/sub x/N/sub y//Ta/sub 2/O/sub 5/ stacked gate oxides on strained-Si

In this paper, we investigate the SiO/sub x/N/sub y//Ta/sub 2/O/sub 5/ gate stack as a possible candidate for future strained-Si CMOS applications and demonstrate and possibility of integration of high-k gate dielectric with the strained-Si.