Records of the 2003 IEEE International Workshop on Memory Technology, Design and Testing

The following topics are dealt with: application specific DRAMs; cost optimum embedded DRAM design; memory test generation for DRAM defects; linked faults analysis in RAMs; reducing test time of embedded SRAMs; testability-driven optimizer and wrapper generator for embedded memories; ITRS commodity roadmap; electrical simulation model for the Chalcogenide phase-change memory cell.