Chip-on-chip technology with copper through-plug for 0.15 /spl mu/m SRAM

SRAM reliability impact and MOSFET electrical characteristics with copper (Cu) through-plug for three-dimensional (3-D) integration are examined and some degradation modes are inspected. Although the initial chip yield of chip-on-chip (COC) sample is comparable to references, the degradation occurs after high-temperature-storage (HTS) test. The degradation due to Cu diffusion could not be found, the mechanism of degradation is explainable in terms of plasma induced damage (PID) by the through-plug process. And it is found that the degradation is not crucial and it can be recovered by sinter process. Consequently, it is confirmed that the proposed COC process is practically effective and reliable. COC process is a promising solution for future high-performance system in package (SIP).