Design and implementation of concatenated decoder

A concatenated decoder mainly composed of depunctured Viterbi decoder, convolutional deinterleaver, and Reed-Solomon decoder is presented. It has very wide applications in DVB, HDTV and satellite communication systems. In the convolutional interleaver, an over-clocking scheme is employed to guarantee the speed limits. The algorithms of Viterbi decoder and RS decoder are modified T-algorithm and modified Euclidean algorithm, respectively. Furthermore, the finite field multipliers and inversion over composite fields was adapted to optimize area and power in RS decoder, which reduced the area near to 25% compared to the conventional finite fields. The proposed concatenated decoder has about 81,000 gates except RAM model, which are implemented in 100 MHz using 0.25 um CMOS process.