Design and modeling of a high-Q on-chip hairpin inductor for RFIC applications

The design and modeling of a high Q hairpin inductor is presented. The inductor is designed and fabricated using the thick top-level metal (4/spl mu/m thickness, 14/spl mu/m away from the substrate) in an IBM 0.5/spl mu/m SiGe BiCMOS process to provide very high peak Q, approaching 27 from 2 to 4GHz, specifically for integrated voltage-controlled-oscillator (VCO) applications. A broadband lumped-element model is also developed for this structure. The modeling methodology is verified using commercial field solvers (IE3D and ADS Momentum) and hardware measured data, the results show that the derived model correlates with the EM simulation data.