Optimized low-power synchronizer design for the IEEE 802.11a standard

The authors propose a low-power synchronizer design for the IEEE 802.11a standard capable to estimate frequency offsets in the range /spl plusmn/468 kHz (80 ppm @ 5.8 GHz) with very simple and effective frame detection and timing synchronization. The core area of the design after layout is 13 mm/sup 2/, including the CORDIC and FFT processors, with a total estimated power consumption of 140 mW.