A new construction of the irreducible polynomial for parallel multiplier over GF(2/sup m/)

This paper presents the construction algorithm of the irreducible polynomial which needs to multiply over GF(2/sup m/) and the flow chart representing the proposed algorithm has been proposed And also, we get the degree from the value of x/sup m.k/ formation to the value of k=7 using the proposed flow chart. The multiplier circuit has been implemented by using the proposed irreducible polynomial generation(IPG) algorithm in this paper, and we compared the proposed circuit with the conventional one. In the case of k=7, one AND gale and five Ex-or gates are needed as the delay time for the irreducible polynomial in the proposed algorithm, but seven AND gales and seven Ex-or gates in the conventional one. As a result, the proposed algorithm shows the improved performance on the delay time.