Towards a user-friendly design and verification environment

We present an environment for the verification of complex concurrent software and hardware systems. The tool is targeted at users who are not necessarily expert in formal methods. The underlying mathematical specification language and verification methodologies are hidden to the user by encapsulating them within a high-level environment that supports graphical design, intuitive specification of properties, high-level data representation, customised interfaces and predefined verification strategies. The semantic base of the tool is given by the Circal process algebra, which allows the internal representation of both the system model and its properties within the same language.