Localization and analysis of functional failures in deep submicron advanced ASIC products

This paper proposes a complete methodology of localizing functional scan failures on complex custom ASIC designs without the need for special test development or use of specialized design debug equipment. The effectiveness of the methodology was proven in the foundry on several ASIC products from two different companies. The results of this work provided necessary information for the FAB manufacturing teams to understand the nature of the problem and resulted in process enhancements, which enabled the FAB to achieve significant yield improvement in record time.