Impact of scaling on the high current behavior of RF CMOS technology

In this paper the impact of the starting material resistivity on the ESD, latch-up and BVii sensitivity is investigated for a sub-0.1 /spl mu/m fully silicided CMOS technology for low power and RF applications. The mechanisms through which a substrate spreading resistance increase enhances the uniformity of the ESD current in nMOS protection methods are investigated in detail.