Characterization of the V/sub T/-instability in SiO/sub 2//HfO/sub 2/ gate dielectrics

The electrical stability of CMOS devices with conventional gate dielectrics is commonly studied using static (DC) measurement techniques. By applying the same methods to MOS devices with alternative gate dielectrics, it has been shown that alternative gate stacks suffer from severe charge trapping and that the trapped charge is not stable, leading to fast transient charging components. In this paper, time-resolved measurement techniques down to the /spl mu/s time range are applied to capture the fast transient component of the charge trapping observed in SiO/sub 2//HfO/sub 2/ dual layer gate stacks. Furthermore, its impact on the device performance and reliability of n-channel FETs is discussed.