20 GHz feedback amplifier design in standard 0.18 /spl mu/m CMOS

The design of feedback networks for high frequency CMOS amplifiers is presented. It is shown that transistor Y-parameters can be used to design high speed CMOS amplifiers with parallel and series feedback networks to improve the maximum available gain and stability. Single-stage common gate amplifiers fabricated in a standard commercial 0.18 /spl mu/m CMOS process are presented at 20 and 23 GHz. The 20 GHz version offers 6 dB of gain and the 23 GHz version offers 3 dB gain.