A novel RAM architecture for bit-plane based coding

Summary form only given. An optimized memory organization has been designed for the hierarchical coding of wavelet subbands. Changing the RAM access pattern and using multiple location access at each clock instant can accomplish a better economy in time and resources. The bit-planes are distributed along the z-direction and the x-y plane contains 256 /spl times/ 256 number of memory elements. The memory plane selection is done by the plane-decoder. Each plane has in turn N /spl times/ N memory units, which are addressed by the row and column decoders, composed of 8 number of 8-to-256 decoders. In the proposed organization, a switching structure is used for selection of the data line. In a 256 /spl times/ 256 image, for EZW or SPIHT coding, the proposed RAM structure requires 8 /spl times/ 32 /spl times/ 256 clocks compared to the conventional RAM that requires more clocks. This shows that the proposed RAM requires much fewer clocks to read the data for bit-plane coding.