PASIC: a smart sensor for computer vision

The processor, A/D converter, sensor integrated circuit (PASIC) prototype chip, which contains 256*256 photosensors, a linear array of 256 A/D converters, two 256 8-b shift registers a 256-bit-serial arithmetic logic unit, and a 256*128-b-dynamic RAM, is presented. It is claimed to be a viable architecture for low-level vision processing. The processors operate in single-instruction multiple-data (SIMD) mode at 20 MHz. When executing an edge-detection algorithm, it is shown that the 256 processors are capable of an output rate of 3 Mpixel/s.<
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