A novel elevated MOSFET source/drain structure

A vertically layered elevated drain structure is proposed which is suitable, in terms of reliability and performance for MOSFET scaling down to the 0.25- mu m level without a reduction of the supply voltage below 3.3 V. In this structure, a low-doped polysilicon or crystalline silicon spacer (layer) is used to solve the hot-carrier problem. In contrast to existing device structures, which try to minimize the impact ionization rate, this structure rests on the idea that high-impact ionization and even high hot-carrier injection (HCl) rates can be tolerated as long as they are not detrimental to the device characteristics.<
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