The hardware implementation of a genetic algorithm model with FPGA

A genetic algorithm (GA) is a robust parallel calculation method based on natural selection, which can be applied to the distributed and concentrated industry optimizing control process. The hardware function of a GA operation can be implemented by an FPGA. In this paper, a hardware implementation method of a GA based on an FPGA is presented. The results of this research can be applied to the study and implementation of evolvable hardware (EHW).