Design of 0.18 /spl mu/m CMOS test chip for package models and I/O characteristics verification

Reliable packages for modern chips are crucial for satisfactory system performance. Once the package is designed for the chip, in order to ascertain its performance, its equivalent electrical model is plugged into simulation decks and its performance characteristics analyzed. However, one implicit assumption designers make is that these equivalent electrical models are accurate for performance characterization of packages. Verification of the accuracy of these models is an objective of this design. Secondly, signal integrity for inter-chip communication is crucial from a systems perspective. To study the signal integrity of data under different PVT conditions, appropriate test structures are needed. Data can be subjected to controlled variations through these structures and its integrity studied. Design of such test structures to subject data to controlled variations have been proposed in this design. Thirdly, testing package reliability at high temperatures is important since on-chip temperatures are increasing dramatically as processes continue to scale. Modelling on-chip temperatures and studying thermal integrity of packages is a goal with this test chip. By analyzing the power supply droop on the test chip under different switching conditions and comparing it with the simulated data, the accuracy of package models can be verified. Furthermore, I/O cells on the chip have been custom designed to test signal integrity across the package and the transmission lines on the board. Additionally, the test chip has daisy chain structures that help analyze thermomechanical properties of the package under non-uniform distribution of heat across the die.