A VLSI implementation of a maximum/minimum coder for low-rate digital communications systems

Custom design VLSI implementation of the maximum/minimum coding (MMC) algorithm is presented. The algorithm decomposition, floorplan, basic cell design, layout, and simulation are discussed. The major subsystems (input buffer, max/min calculator, output buffer, control PLAs) are presented. The resulting chip design is composed of 40000 CMOS transistors with 2.5 mu m linewidth technology. Computer-aided design (CAD) tools and CAD platforms are discussed, emphasizing the relevant areas for custom VLSI design in higher education.<
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