Register allocation for GaAs computer systems

When a VLSI processor is to be implemented using gallium arsenide rather than silicon technology, register allocation becomes far more important to the efficiency of the complete system. A novel graph-based scheme for finding the minimum execution-time register allocation is presented. Since arbitrary cost functions can be associated with various references and spilling conditions, this model can guarantee optimal register allocation for minimum execution time. With a small number of registers available, GaAs system performance can be greatly improved by optimal, as compared to traditional, register allocation. Moreover, the computational complexity of the proposed register allocation method is no worse than that of the standard graph-coloring technique.<
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