Analog timing recovery for a noise-predictive decision-feedback equalizer

A timing recovery architecture and its CMOS implementation are described for a noise-predictive decision-feedback equalizer (NPDFE). The 0.5-μm CMOS prototype includes timing recovery and the NPDFE and operates at 160 Mbit/s. The timing recovery blocks dissipate 27 mW from 3.3 V, occupy 0.2 mm
²
, and achieve a root mean square jitter of 50 ps, which is 0.8% of a bit period.