A CMOS high-speed wide-range programmable counter

A CMOS high speed wide-range programmable divide-by-N counter was designed and the performance was verified by SPICE simulations and the measurements on the fabricated chip. A new reloading scheme and the use of simplified circuits for three least significant bit flip-flops enabled the high-speed operation of the proposed counter, independently of the number of counter stages. The proposed and Chang's counters were fabricated on the same chip using a 0.6-/spl mu/m triple-metal CMOS technology. The proposed and Chang's counters with six stages were measured to work up to the clock frequencies of 1.34 GHz and 930 MHz, respectively.