High-speed architectures for dynamic programming problems

Concurrent fine-grain pipelined VLSI architectures for dynamic programming (DP) problems are presented. Look-ahead is used to obtain finer-grain pipelining, and a novel precomputation sequence is used to design DP computation architectures with square to linear add-compare-select (ACS) processor complexity (in number of states in the DP problem). Use of nonuniform pipelining and nonuniform implementation methodologies in dedicated DP architectures is introduced; this results in a saving of hardware modules with no loss in speed. A two's complement least-significant-bit-first bit-serial architecture is also presented for the compare-select operation.<
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