Circuit technologies for 16Mb DRAMs

THIS PAPER WILL DESCRIBE circuit technologies not only necessary for submicron ULSl memories, but also for customized ULSIs including RAM blocks. Key circnlts proposed here are an on-chip error checking and correcting (ECC) circuit that induces little access penalty, and sense circuits suitable for fast data- sensing at 3.3V operation. A 16Mb CMOS dynamic RAM incorporating a main sub bitline structure and 4.9μp2 Isolation Merged Vertical Capacitor (IVEC) cells has been designed and fabricated using a 0.7μm CMOS process as a test vehicle for these circuits