A GaAs 16 × 16b parallel multiplier using self alignment technology

THIS report will cover a gAaS 16 X 16 bit parallel multiplier using direct coupled FET logic (DCFL) circuit with tungsten-silicide gate self alignment technology. The chip contains 3168 gates with 2μ gate length enhancement/depletion FETs. Multiplication was performed in 10.5ns, with a power dissipation of 952mW at a supply voltage of 1.6V.