Automatic generation of digital cell libraries

This paper presents cell design flow - CDF, a tool for automatic generation of digital cell libraries. It is able to synthesize physical layouts of logic cells from truth table descriptions or Boolean equations. The tool is also able to generate a complete set of cells according to boundary conditions, such as the maximum number of cell inputs and the maximum number of serial transistors. The libraries provided by CDF are compatible to professional IC design environments, like Cadence and Mentor Graphics.